I am not sure, but drain and source connections shouldn't matter too much, rather the bulk of the transistors.
Group same NMOS (A,B) and same PMOS (C,D) transistor pairs, like this:
my array is only NMOS transistors and E is normal transistor not a dummy.
by any way either mine or your array is a two side connection to connect the upper side terminals to the the down transistors terminal.
Since I have 5 transistors, I used 10 horezontal wires up and the same down... then the matched array becomes very big, most of it is dominated by the wiring. I am thinking by this way it will add large parasatics. How in literature suggest to connect higher order of arrays, I really doubt it.
May be I will support my question with image as soon as possible
Read papers about D/A Converters. There is a lot of stuff how to deal with layout effects for large number of matched transistors - both for dc like for high speed optimization.