exp
Full Member level 1
Hi,
I understanding Frie's equation, maximum power theorem etc for a conventional receiver. However, do I understand it right that all this is based on the fact that we assume a given input power?
Suppose I can pick the power level of my input signal arbitrarily (only limited by linearity/swing) and after the ADC I want a certain end-to-end SNR of say -45 dB. Would the NF in this case matter at all?
(Reason: My signal is actually a transmitter output and hence 40-50dBm, hence I even need to atternuate it to make it compatible with my receiver)
1.) An ADC is known for its horrible NF, say 30dB. A conventional receiver would add LNA & gain in order make the overall NF much lower (through Frii's), say 5 dB. However, these gain stages add noise themselves. So if I assume the maximum input swing of my ADC is 2Vpp (13 dBm) and I can pick my input power level of the receiver arbitarily, is there any way to beat connecting the ADC straight to the source, despite having a high NF of 30 dB?
2.) What is the actual reason I want to match? Yes, for maximum power transfer ... but the actual reason? Say, the source has a conventional 50 Ohm source resistance and I design my receiver with, say Rin=1k. Then the noise power at the input of the receiver would be 4kT50(1000/(50+1000))^2 1/1000 ~ 4kT50/1000 ... 250x smaller than with matching and ... since I can choose the power at the input anyway ... it would not matter.
3.) Some numbers: As indicated, I need end-to-end SNR of 45 dB and I have 800 MHz. So the total integrated noise floor alone is -85 dBm. So I have "SNR = 45 = Pin + 85 - NF". Combining I get "Pin = -40 + NF. Assuming the 30dB NF ADC as mentioned above, this would be Pin >= -10 dBm! Pretty high number, specifically for 1VDD technologies where the maximum swing is maybe 500mV and hence 7 dBm.
3.a.) Same as question 1) but with numbers: Is there anything I can do to improve the SNR (e.g. picking a lower Pin but some amplification)?
3.b.) I want to do some analog system signal processing before the ADC, speficially mixing and integrating. Now I could set the unity-crossover frequency of the integrator to the bandwidth, 800 MHz and add enough gain to do the integration. But I could also set the unity crossover frequency much lower and use a high input power instead. In that case, there would be a passive RC (and low gain) in front of the ADC (which would attenuate) the signal. However, I can pick it as high as permitted by the input/output swings (~7dBm). Is there any way to beat this scenario by adding gain stages or can I say it's always best to do the least work if the input power can be chosen arbitrarily?
I understanding Frie's equation, maximum power theorem etc for a conventional receiver. However, do I understand it right that all this is based on the fact that we assume a given input power?
Suppose I can pick the power level of my input signal arbitrarily (only limited by linearity/swing) and after the ADC I want a certain end-to-end SNR of say -45 dB. Would the NF in this case matter at all?
(Reason: My signal is actually a transmitter output and hence 40-50dBm, hence I even need to atternuate it to make it compatible with my receiver)
1.) An ADC is known for its horrible NF, say 30dB. A conventional receiver would add LNA & gain in order make the overall NF much lower (through Frii's), say 5 dB. However, these gain stages add noise themselves. So if I assume the maximum input swing of my ADC is 2Vpp (13 dBm) and I can pick my input power level of the receiver arbitarily, is there any way to beat connecting the ADC straight to the source, despite having a high NF of 30 dB?
2.) What is the actual reason I want to match? Yes, for maximum power transfer ... but the actual reason? Say, the source has a conventional 50 Ohm source resistance and I design my receiver with, say Rin=1k. Then the noise power at the input of the receiver would be 4kT50(1000/(50+1000))^2 1/1000 ~ 4kT50/1000 ... 250x smaller than with matching and ... since I can choose the power at the input anyway ... it would not matter.
3.) Some numbers: As indicated, I need end-to-end SNR of 45 dB and I have 800 MHz. So the total integrated noise floor alone is -85 dBm. So I have "SNR = 45 = Pin + 85 - NF". Combining I get "Pin = -40 + NF. Assuming the 30dB NF ADC as mentioned above, this would be Pin >= -10 dBm! Pretty high number, specifically for 1VDD technologies where the maximum swing is maybe 500mV and hence 7 dBm.
3.a.) Same as question 1) but with numbers: Is there anything I can do to improve the SNR (e.g. picking a lower Pin but some amplification)?
3.b.) I want to do some analog system signal processing before the ADC, speficially mixing and integrating. Now I could set the unity-crossover frequency of the integrator to the bandwidth, 800 MHz and add enough gain to do the integration. But I could also set the unity crossover frequency much lower and use a high input power instead. In that case, there would be a passive RC (and low gain) in front of the ADC (which would attenuate) the signal. However, I can pick it as high as permitted by the input/output swings (~7dBm). Is there any way to beat this scenario by adding gain stages or can I say it's always best to do the least work if the input power can be chosen arbitrarily?