johnmdouglas
Newbie level 4
Hi there,
I am trying to find a solution for massive throughput (1 GB/ns) combined with low latency (10 ns) for a digital ASIC. The chip is part of a parallel application from a scientific project. I need to compute rapidly a lot of data in parallel. I looked at DDR2/3 and it is not much for what I need. DDR4 is supposed to have improved throughput (point-to-point channels) but it still far from what I need.
Is it possible to create on a board 128 sockets of DDR3, split in groups of 2 (i.e. 64 groups), where each group is using a separate MAC & PHY cores, so that each parallel computation module will access only one DDR group. I guess that would increase the throughput.
Is there any other solution out there?
Thanks,
John
I am trying to find a solution for massive throughput (1 GB/ns) combined with low latency (10 ns) for a digital ASIC. The chip is part of a parallel application from a scientific project. I need to compute rapidly a lot of data in parallel. I looked at DDR2/3 and it is not much for what I need. DDR4 is supposed to have improved throughput (point-to-point channels) but it still far from what I need.
Is it possible to create on a board 128 sockets of DDR3, split in groups of 2 (i.e. 64 groups), where each group is using a separate MAC & PHY cores, so that each parallel computation module will access only one DDR group. I guess that would increase the throughput.
Is there any other solution out there?
Thanks,
John