masking/disabling selected timing violation in GLS in VCS

[vcnvcc]

Hello,

what is the issue -
in my GLS run I see many timing violations, now on selected port/module I wanted to disbale/mask any setup/hold/recovery/removal violation.
Question is how do I do that? what command I use? and how I use that command? In VCS

I have checked related site, and internet,

I came across notimingcheck. But is this command can be used for selected port/module? if yes how to use? any eg/syntax?

I came across tcheck command, which is related to ucli. Here I am confused - i have some sub questions
- i know full form of UCLI, but how it is related to VCS
- can I use ucli with vcs? if yes when i can use it? & how?

There are members who are experienced & who has used it frequently- thats why i am posting it over here... Thanking you all

please share your inputs/comments/ideas..

 

[maulin sheth]

Hello,
notimingcheck is disable the whole circuit timing check,means it will not take SDF at input ,it is used for the unit delay simulation.

You can do like :
1) force the input using the verilog file for particular time,by doing this you are not disabling any violation but just making constant for partiucular pin for particular time.
u can force any instance inside the chip.
2) if you want to do for just test purpose,thn just change the SDF w.r.t your requirement,thn do the simulation again.

Can I know why you want to disable the timing check for port/module..means what is the main objective/purpose to do this?