I am using synopsys DC ultra (topo) for synthesis with provided reference methodology by synopsys,
However, aftert synthesis I got netlist with GTECH components,
How can I map my design to Technology library ?
Hi Bhargav,
In synopsys you have .synopsys_dc_setup file. In this file you have to specify your link and target library in order to map your logic to actual library. If you don't specify any library as target and link lib. it will map the logic is its standard GTECH library(generic tech library).
Hope this will solve your problem.......