module AESEncryptor(InputPlainText, InputPassword, OutputCipherText, clk, rst_n
);
input clk,rst_n;
input [127:0] InputPlainText;
input [127:0] InputPassword;
output reg [127:0] OutputCipherText;
// Storing Values in RCON LUT
reg [7:0] RCON [0:9];
// PlainText stores the plain text as an 8x176 RAM
reg [7:0] PlainText [0:175];
// RoundKeys is the 8x176 RAM for storing the RoundKeys
reg [7:0] RoundKeys [0:175];
// tempRoundKey for storing a 4 byte number (in RoundKey process)
reg [7:0] tempRoundKey [0:3];
reg [7:0] CipherText [0:15];
integer i,j=0;
initial
begin
// initializing RCON register
RCON [0] = 8'h01; RCON [1] = 8'h02; RCON [2] = 8'h04; RCON [3] = 8'h08;
RCON [4] = 8'h10; RCON [5] = 8'h20; RCON [6] = 8'h40; RCON [7] = 8'h80;
RCON [8] = 8'h1b; RCON [9] = 8'h36;
end
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
for (i=0;i<16;i=i+1)
CipherText [i] = 0;
end
// storing password into 16x8 RAM
// storing the initial 16 bytes RoundKeys in a RAM
else
begin
// Storing the password as the first 16 bytes of Roundkey
// Converting the Input Plain Text into 8x16 bytes of RAM
for (i=0;i<16;i=i+1)
begin
RoundKeys [i] = InputPassword [(8*(i+1)-1)-:8];
PlainText [i] = InputPlainText [(8*(i+1)-1)-:8];
end
//*****************Initial Round****************
end
end
endmodule
Among the many issues in your code, the main one is that you do not output anything from the module (i.e. OutputCipherText is never assigned). Therefore the synthesizer will consider every other signal to be superfluous and remove the logic. Thus, no design.
r.b.
Among the many issues in your code
r.b.
Hi
1) Initial statements are not often used in synthesizeable code, I know for a fact that what you have written will not work at all if synthesized in Synplify Pro. In hardware, there is no magic way to have memory arrays start up in a specific state. This must be directed by you, the hardware designer. If it is an array of flip flops, you should reset them to your desired state using the reset signal, as you have done for some of the other arrays. If the LUT is going to be a compiled memory, then the vendor will have some method for you to specify a non-zero power up state (i.e. memory initialization file or similar). I believe it may be possible to specify a $readmemh command in an initial block and have it synthesize correctly, but I have never tried it. I prefer to write code to explicitly describe the way I would like things set up.
I disagree with initial statement with flip flops. Xilinx (and i think in 99% altera) fully support initialization to '1' or '0'. Xilinx even recommend it in one white paper that, if engineer add reset signal just to put dff into known state after booting the device to use signal initialization instead and remove reset from your design to relax routing and implementation constraints.
Code Verilog - [expand] 1 2 3 4 5 6 reg some_flipflop = 1'b0; // properly initialized after configuration using the global reset // note the total lack of reset in here always @(posedge clk) begin some_flipflop <== something; end
This topic comes up every once in a while, and I suspect not everyone will agree on the above. But I have yet to hear a compelling argument on why one would use an explicit reset for all flip-flops in a design targeting fpga.
I'm not able to go search for it right now, but when I have time I'll go look for that paragraph and post details.
Inferred Power-Up Levels
Quartus II Integrated Synthesis reads default values for registered signals defined in Verilog HDL and VHDL code, and converts the default values into Power-Up Level settings. The software also synthesizes variables with assigned values in Verilog HDL initial blocks into power-up conditions. Synthesis of these default and initial constructs allows synthesized behavior of your design to match, as closely as possible, the power-up state of the HDL code during a functional simulation.
The following register declarations all set a power-up level of VCC or a logic value “1”, as shown in this example:
signal q : std_logic = '1'; -- power-up to VCC
reg q = 1'b1; // power-up to VCC
reg q;
initial begin q = 1'b1; end // power-up to VCC
Both links are essentially focussing on the same point, it's the undefined timing relation between reset release and clock that causes the problems.This was one of the knowledge base articles I read about this subject. I couldn't find the other article and I haven't looked in the documentation for the corresponding information.
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