I don't understand the reference to "thick metal". The quoted link is discussing a lossless TL with variable C load. If "thick" means increased center conductor diameter or microstrip width, it results in reduced ZL, hence the opposite of "wL >>R".
If the question is related somehow to a real circuit design problem, what are fixed and variable parameters? In most cases, CL is fixed (not considering intentional increase), also transmission line length. ZL can be varied within tight limits, e.g. 40 - 80 ohms in a PCB design, Rs can be varied over a wider range.
Following impedance matching rules, you'll choose Rs = ZL and get a perfect first order transition with capacitive load. Risetime is however limited by Rs*Cload time constant. With Rs < ZL, you get overshoot and a certain ringing, rise time is however reduced. If short rise time is your major objective, you may want to accept a certain (10 -20 %) overshoot.
Suggest to use a circuit simulator like LTspice and simulate the discussed setup.