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Making output of one module the other one's clock

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yttuncel

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Hello,

I am modifying a simple keyboard interface I found on the net. The idea is whenever there is a new scancode, it will make the output named "Scan_Dav" go high, and then go low. So when I direct Scan_Dav to another module as a clock, that module's clock will have a rising edge whenever a new ScanCode is pressed. Is there any error in my way of thinking? If there is none, I will put my codes and ask you why what I made is not working. Thanks
 

TrickyDicky

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I wouldnt recommend doing that. Using logic generated clocks can cause all sorts of timing problems. it would be best to clock the sub module at the system clock and build a rising edge detector.
 

yttuncel

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I tried it the other way around but it did not work. It was like this:


Code VHDL - [expand]
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if rising_edge(clk) then
    if Scan_Dav = '1' then
    -- do the shifting here
    end if;
end if;



EDIT: Also, I want to wait till someone presses Enter to scroll the text. So until enter is pressed, the text is to shift by one digit only when a new scancode is arrived.
 
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K-J

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I tried it the other way around but it did not work. It was like this:

Code:
if rising_edge(clk) then
   Scan_Dav_Sync(0) <= Scan_Dav;
   Scan_Dav_Sync(1) <= Scan_Dav_Sync(0);
   Previous_Scan_Dav <= Scan_Dav_Sync(1);
   if (Previous_Scan_Dav = '0') and (Scan_Dav_Sync(1) = '1') then
      -- do the shifting here
   end if;
end if;
EDIT: Also, I want to wait till someone presses Enter to scroll the text. So until enter is pressed, the text is to shift by one digit only when a new scancode is arrived.
Above code has been edited with the following changes
- Scan_Dav_Sync added to synchrnoize the Scan_Dav input to the clock
- Previous_Scan_Dav added to store the previous state so that the 'rising edge' (i.e. used to be low, now it's high) of Scan_Dav can be detected

Kevin Jennings
 

yttuncel

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I got the idea here, but what changes implementing like this will make? Also I need to use the board's clock with this one right? I will update here after I try what you suggested. Thank you KJ

UPDATE: I tried what is suggested. Below is the code


Code VHDL - [expand]
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signal bytes : std_logic_vector(63 downto 0);
signal Scan_Dav_Sync: std_logic_vector(1 downto 0):="00";
signal Previous_Scan_Dav: std_logic:='0';
begin
    process (clk) begin --clk is 50 MHz
        if rising_edge(clk) then
             Scan_Dav_Sync(0) <= Scan_Dav;
             Scan_Dav_Sync(1) <= Scan_Dav_Sync(0);
             Previous_Scan_Dav <= Scan_Dav_Sync(1);
             if (Previous_Scan_Dav = '0') and (Scan_Dav_Sync(1) = '1') then
                 bytes <= bytes (bytes'high-8 downto 0) & Data_in;
             end if;
          end if;
    end process;


I used 50 Mhz clock. Still this inserts 2 "Data_in"s, and shows 2 of each letter on seven segment display. Do you wish to have a look at where Scan_Dav comes from, maybe that is the source of the error?

EDIT: What could be the reason keyboard controller reads data 2 times? and thus changing scan_dav 2 times?
 
Last edited:

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