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MAking a core of my VHDL project

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John_Sanders

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Dear All

Is it possible to make a soft core for my project which i designed using VHDL. i mean that if i need to share the synthesized project, i don't need to share the code just the softcore; the output and input pins of which are only visible and not any part of coding. Please help me guys its urgent

i used Xilinx ISE design suite to make my project on spartan 3e 1200k


Thanks
 

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