Make the frames visible on VGA port via FPGA.

[MSPnanu]

I have got to interface C3088 camera with Xilinx Spartan 3E FPGA. I have 8 outputs, [7:0]Y from camera, connected to FPGA. I used Strata Flash memory to store the frames as the camera has 352*288 pixels. Now, I want to display the content in memory to VGA port. How to display in monitor. Please Help. Searched net, but couldn't find the answer I am looking for.

 

[TrickyDicky]

You'll need a VGA controller, and probably a standards conversion block - which will required external memory.

 

[MSPnanu]

You'll need a VGA controller, and probably a standards conversion block - which will required external memory.

I have data stored in Strata Flash memory. These data are 8bits data in 101375 memory locations (352*288 pixels from camera). So, how can I take the data from memory and display the same in VGA? Is it possible?

This is my code in Verilog:

module frame2vga(clk,pclk,yin,red,green,blue,href,vsync);
input wire [7:0]yin;
input wire clk;
input wire pclk;
output reg red;
output reg green;
output reg blue;
output reg href;
output reg vsync;
reg clkout;
reg video_on_h;
reg video_on_v;
reg horiz_sync;
reg vert_sync;
reg pclk_sync;
reg video_on;
integer h_count=0;

//reg clk25;
always@(posedge clk)
begin
clkout=~clkout; //25MHZ clock for VGA
end
//reg [8:0] counterx;
//reg [8:0] countery;
integer counterx=0;
integer countery=0;
integer v_count=0;

wire CounterXmaxed = (counterx==352);
//parameter check_horizsync=4'b0001,check_vertisync=4'b0010;
//reg[3:0]crt,nxt;

always @(posedge clkout) begin
pclk_sync<=pclk;
end
always @(posedge pclk_sync)
begin
if(CounterXmaxed)
counterx <= 0;
else
counterx <= counterx + 1;
if(CounterXmaxed)
countery <= countery + 1;
if(countery==288)
countery<=0;
end
always@(posedge clkout)
begin
if(h_count==799)
h_count=0;
else
h_count=h_count+1;
if (h_count<= 755 && h_count >=659 )
horiz_sync<=0;
else
begin
if (counterx< 352 && counterx>0)begin
video_on_h=1;
horiz_sync<=1;end
else
video_on_h=0;
end
if (v_count >= 524 && h_count >= 699)
v_count<=0;
else if (h_count==699)
v_count<= v_count + 1;
if (v_count <= 494 && v_count >= 493)
vert_sync<=0;
else
begin
if (countery < 288 && countery>0) begin
video_on_v =1;
vert_sync<=1; end
else
video_on_v =0;
end
video_on=video_on_h & video_on_v;
if (video_on==1)
begin
red=1'b1;
green=1'b1;
blue=1'b1;
end
else
begin
red=1'b0;
green=1'b0;
blue=1'b0;
end
href<= horiz_sync;
vsync<= vert_sync;
end
endmodule

Here, I assumed that every pclk_sync means every rise of pixel. But, I think my logic is wrong. Do you have any idea?

 

[TrickyDicky]

like I said, you will need a VGA controller and standards converter. I suggest reading up on how VGA works
https://en.wikipedia.org/wiki/Video_Graphics_Array

 

[MSPnanu]

like I said, you will need a VGA controller and standards converter. I suggest reading up on how VGA works
https://en.wikipedia.org/wiki/Video_Graphics_Array

Yaa, thanks. I know how VGA works, but I am really unable to display even one line from memory to VGA via FPGA.

 

[TrickyDicky]

Well for a start, you should not use a logic generated clock. Either use a PLL to divide the clock by two and pass the data through a fifo, or use clock enables and clock evberything on the system clock.

Secondly, I dont know what the problem is - have you testbenched it? does it create the correct VGA timings?