Mains zero cross circuit

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cupoftea

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Hi,

We need a zero cross circuit which gives a falling edge 430us +/-50us before the zero cross. The attached is the best we can come up with. Do you have better?

Its for 100VAC +/-15%

LTspice and jpeg attached
 

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KlausST said:
The PLL needs to precisely lock on a 1:12 input frequency range. But this is a different challenge.
Click to expand...
The advantage of the Type II PD being edge-sensitive (dual D FF) makes it both a phase+frequency detector to have a capture range equal to the entire range of the VCO. This disadvantage is a dead-zone from latency.

Tony
 
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Basic law of capacitor behavior: series cap advances sinewave current.

Values in the simulation work for 500 Hz. Voltage across the anti-parallel diodes crosses zero at a point 450 uSec preceding the source. Experimentation will reveal what RC values work at other frequencies.

 
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