MachXO external clock question

[sgergo]

Hi!

I'm a beginner in programmable logic and I'm trying to learn by experimenting on small projects using a Lattice MachXO Breakout Board which has MachXO2280 sitting on it. Unfortunately, MachXO seems to changed to NRND thus there is not much documentation around and the Lattice site is pretty poor too. I'm using Lattice Diamond as an IDE.

I'd like to use an external clock source - a 25 MHz TCXO - as the primary clock source of the CPLD. What I can do now is to feed the oscillator output into a random I/O pins and it is all well but I learned that I should feed the external clock signal into a dedicated clock pins to get a nice, undelayed clock signal Indeed, there are PCLK pins but I'm not sure how to configure them: it is just hooking up the TCXO's output to any of the PCLK pins and selecting that pin in the spreadsheet or is there anything else to change in Diamond? Since there are no examples I'd be really appreciated if someone could help. Thank you!

 

[aruipksni]

Hi!

I'm a beginner in programmable logic and I'm trying to learn by experimenting on small projects using a Lattice MachXO Breakout Board which has MachXO2280 sitting on it. Unfortunately, MachXO seems to changed to NRND thus there is not much documentation around and the Lattice site is pretty poor too. I'm using Lattice Diamond as an IDE.

I'd like to use an external clock source - a 25 MHz TCXO - as the primary clock source of the CPLD. What I can do now is to feed the oscillator output into a random I/O pins and it is all well but I learned that I should feed the external clock signal into a dedicated clock pins to get a nice, undelayed clock signal Indeed, there are PCLK pins but I'm not sure how to configure them: it is just hooking up the TCXO's output to any of the PCLK pins and selecting that pin in the spreadsheet or is there anything else to change in Diamond? Since there are no examples I'd be really appreciated if someone could help. Thank you!

yes you need to connect to the closest dedicated clock pad if possible. then you can use internal PLL.

 

[sgergo]

yes you need to connect to the closest dedicated clock pad if possible. then you can use internal PLL.

Okay, but correct me if I'm wrong: these clock pads have dual function: clock input and GPI/O. How would the CPLD know that the connected pad should be in clock input mode? As I mentioned I was able to input the 25 MHz oscillator signal into any GP I/O pins with no problem but I'm afraid this is not the right way to provide clock source to the CPLD,,,:-(

 

[mrflibble]

You usually have a constraint file that tells the tools what net to connect to what IO pin, and also what signal standard etc to use...

 

[aruipksni]

You usually have a constraint file that tells the tools what net to connect to what IO pin, and also what signal standard etc to use...

yes, the lattice diamond has a spread sheet view, in which you assign pins and functions.
this you can export to a pin layout file, that you can edit outside the tool, and import back.
you can check the lattice videos :
https://www.latticesemi.com/en/Products/DesignSoftwareAndIP/FPGAandLDS/LatticeDiamond.aspx