Re: LVS wired problem in Cadence,
Sometimes circuits with a lot of identical looking "stuff" that
is repeated, will make LVS confused. This can be totally "luck
of the draw", all about how it recognizes sections as it goes
about netlisting and such.
A layout that is the same at the polygon level, but just
different in some way, could pass where another fails. That's
just the breaks. A layout with pins and a layout without
pins, falls in this situation. LVS is left to decide what the
pin connections are, and it's OK with that - but not OK
with pins asserted?
Seems to me that maybe there's some pin issue or the
schematic matches the "subcircuit" but not the "controller"
(maybe pins, signal nets, power globals, ???). Maybe a pin
ended up misplaced and named some net wrongly.
You can fix it by asserting "correspondence points" (if the
layout and schematic do indeed match) but that effort is
a real nuisance.