LVS problem - Assura - .18um TSMC

[eng]

assura tolerance setting

Hi all,
I'm doing an LVS on a .18um TSMC Buffer circuit by using assura. I got device parameter mismatch errors. I used Layout XL and auto generated all transistors from schematic namely whatever instance exists on the layout is its correspondence in schematic. Although the parameter deviation is very minor, I wonder why it is happening. Does anybody have an idea on this issue?

Here is Assura LVS Error log:

===== Parameter Mismatches for Instances =====
= = = = = = = = = = = = = = = = = = = = = = = =
(param 1)
Schematic Instance: M2 pmos2v
Layout Instance: avD693_2 P

w 6e-06 vs 6e-06 differs by 3.53709e-06%
l 1.8e-07 vs 1.8e-07 differs by 3.79118e-07%

= = = = = = = = = = = = = = = = = = = = = = = =
(param 2)
Schematic Instance: M1 pmos2v
Layout Instance: avD693_1 P

w 6e-06 vs 6e-06 differs by 3.53709e-06%
l 1.8e-07 vs 1.8e-07 differs by 3.79118e-07%

= = = = = = = = = = = = = = = = = = = = = = = =
(param 3)
Schematic Instance: M3 nmos2v
Layout Instance: avD648_2 N

w 2e-06 vs 2e-06 differs by 2.52476e-07%
l 1.8e-07 vs 1.8e-07 differs by 3.79118e-07%

= = = = = = = = = = = = = = = = = = = = = = = =
(param 4)
Schematic Instance: M0 nmos2v
Layout Instance: avD648_1 N

w 2e-06 vs 2e-06 differs by 2.52476e-07%
l 1.8e-07 vs 1.8e-07 differs by 3.79118e-07%

==================================
====== Summary of Errors ======

Schematic Layout Error Type
--------- ------ ----------
4 4 Parameter Mismatches for Instances

 

[gurumallesh j]

assura tolerance setting lvs

hey i to working on lvs for lasi on drc 0.18um and 0.13um will you able get me 0.18um and 0.13um to me. as i find solution i will promise to reply and help u.

 

[Hughes]

lvs error tsmc

I didn't use Assura, but from the report, I guess the rule deck has some bug. Maybe it compare two floating point (the device's parameter) directly.

 

[HanGu]

I think you need look the command file,may be the problem occure at the device extraction section.

 

[Vamsi Mocherla]

Well, you need to tweak the device comparision tolerance. Try and increase it, these errors should vanish.......

 

[limingchou]

i don't use assura. wheter there a grid dot question in the layout design, the min grid dot is mismatch the design rule.

 

[Question]

I have the same problem as you. If you use resistor in your layout, the mismatch may be bigger. I think it becaues the rule of TSMC extraction.

 

[pi331133]

I also encountered this problem before. The LVS log may not point out the real problem, sometimes due to the wrong connection in layout the LVS may mix the device, that is it may considerate device A to match layout B, in fact the parameter of device A and layout A is correct. So this is more like a connection problem, try to delete the connection in layout and schematic, do a lVS it should pass if the conversion from sehcmatic to layout XL is correct.

 

[adrescuer]

Hi

You can specify a tolerance for each parameter in assura rule files.
For instance if you specify 10% tolerance for W of transistors,
W1=10 and W2=9.9 will be matched.

Look at rule files, You can find and modify it.

Bye

ADrescuer

 

[disney]

Also you can specify tolerance under Options -> layoutXL for VXL.
Also look what you have set for "lxRounding" and what is your "aelPushSignifDigits" is set to ?

These 2 places take care of tolerance.
Send me your tsmc18 assura deck and XL Options, I will fix for you