Chinmaye
Full Member level 3
Dear all,
I am trying to perform LVS for the layout I generated in innovus. I am using the OA format to import the layout from innovus to virtuoso. I have no problem with that. I ran DRC on the layout and it worked. Now here is my doubt. I require a schematic netlist to perform LVS. I have generated the layout of my design by writing a verilog code and synthesizing it. Where do I find the netlist required for LVS? Can someone guide me as to how I can proceed further?
TIA
I am trying to perform LVS for the layout I generated in innovus. I am using the OA format to import the layout from innovus to virtuoso. I have no problem with that. I ran DRC on the layout and it worked. Now here is my doubt. I require a schematic netlist to perform LVS. I have generated the layout of my design by writing a verilog code and synthesizing it. Where do I find the netlist required for LVS? Can someone guide me as to how I can proceed further?
TIA