# LVS in calibre for a layout generated in innovus

#### Chinmaye

Dear all,
I am trying to perform LVS for the layout I generated in innovus. I am using the OA format to import the layout from innovus to virtuoso. I have no problem with that. I ran DRC on the layout and it worked. Now here is my doubt. I require a schematic netlist to perform LVS. I have generated the layout of my design by writing a verilog code and synthesizing it. Where do I find the netlist required for LVS? Can someone guide me as to how I can proceed further?
TIA

#### ThisIsNotSam

export a netlist from innovus. the command is something like saveNetlist. it is even present in the GUI under file->save or similar

### Chinmaye

points: 2

#### Chinmaye

export a netlist from innovus. the command is something like saveNetlist. it is even present in the GUI under file->save or similar
I am completely new to this. Could you please point me to a link which has a step by step procedure for this?

#### ranaya

##### Member level 5
I am completely new to this. Could you please point me to a link which has a step by step procedure for this?
In Innovus, after finishing all steps, do following :
1. saveNetlist ${DESIGN_NAME}PostLayout.v Then 2. In IC CWI, create a new library for the design. Attach it to the correct technology (i.e. tsmc 65nm). 3. File -> Import -> Verilog (Assuming the standard cells are already available in your Cadence library manager) Here specify your post layout verilog file. Then the specify the newly created library for your design as the "Target Library". Specify the standard cell library and other basic libraries (if required) in "Reference Libraries" field. 4. Import the netlist. Now the std cells of your designs are available in a schematic. If the VDD/VSS pins are not connected to the global power lines, there is a nice tool called CCSAddWireToPin() from Cadence. Using this, you can connect VDD/VSS and well contacts of the cells globally to power lines in the schematic. Anuradha Chinmaye ### Chinmaye points: 2 Helpful Answer Positive Rating #### Chinmaye ##### Advanced Member level 4 In Innovus, after finishing all steps, do following : 1. saveNetlist${DESIGN_NAME}PostLayout.v
Then
2. In IC CWI, create a new library for the design. Attach it to the correct technology (i.e. tsmc 65nm).
3. File -> Import -> Verilog (Assuming the standard cells are already available in your Cadence library manager)
Here specify your post layout verilog file. Then the specify the newly created library for your design as the "Target Library". Specify the standard cell library and other basic libraries (if required) in "Reference Libraries" field.
4. Import the netlist. Now the std cells of your designs are available in a schematic. If the VDD/VSS pins are not connected to the global power lines, there is a nice tool called CCSAddWireToPin() from Cadence. Using this, you can connect VDD/VSS and well contacts of the cells globally to power lines in the schematic.

Thank you Anuradha for the steps. Here is what I have done so far.
1. I have created a library and imported the lef and gds files in virtuoso.
2. I have created a digital layout in the same library in innovus in OA format. With this, I am able to import the layout from innovus to virtuoso.
3. DRC check is clean.
4. As you said, after routing I shall import the netlist.
But I wanted to know if there is any way where I can check the layout at the block level? Since there cannot be any errors in the standard cells layout, Is it not enough if I check the connectivity between the blocks?
Please correct me if I am not correct.

Also, when I run the command, saveNetlist after layout, I get the netlist file almost similar to the one after synthesis. Can i use the same netlist file after synthesis for LVS in calibre?

Thank you.

Last edited:

#### ranaya

##### Member level 5
But I wanted to know if there is any way where I can check the layout at the block level? Since there cannot be any errors in the standard cells layout, Is it not enough if I check the connectivity between the blocks?
Please correct me if I am not correct.
I don't know what is your exact requirement. Do you have a full chip design with IO pads etc ? Or is it like a smaller one i.e. multiplier, processor etc ? Then shouldn't you just look at running a gate level simulation with layout extracted .sdfs in digital domain ? If the functionality is right and if there were no connection violations observed in Innovus, that would be sufficient. Don't you think ?

#### Chinmaye

I don't know what is your exact requirement. Do you have a full chip design with IO pads etc ? Or is it like a smaller one i.e. multiplier, processor etc ? Then shouldn't you just look at running a gate level simulation with layout extracted .sdfs in digital domain ? If the functionality is right and if there were no connection violations observed in Innovus, that would be sufficient. Don't you think ?

Thanks for the reply. My digital design is basically a small one which has to be merged with a analog layout. Before that i wanted to check the functionality of the layout that is generated from innovus by importing it to virtuoso. I was able to import the layout to virtuoso in OA format and now i want to make sure the functionality is as expected before i merge it with the analog layout. Please suggest how can i go about it.

#### ranaya

##### Member level 5
Before that i wanted to check the functionality of the layout that is generated from innovus by importing it to virtuoso.
For the digital layout alone, running a switching activity simulation is sufficient. So you generate the netlist, .sdf file for the corner of interest (i.e. Typical) AFTER the parasitic/delay extraction at POST ROUTE stage. Then use Modelsim/NCSIM or whatever the preferred RTL simulator to verify it (like we normally do in gate-level simulation). This is the easiest thing to do if you do not want to struggle in transistor-level simulation.

If you want to see the impact of your digital layout on the analog side (glitching, coupling etc), then you have to import the full design in Vertuoso.

Cheers

#### Chinmaye

For the digital layout alone, running a switching activity simulation is sufficient. So you generate the netlist, .sdf file for the corner of interest (i.e. Typical) AFTER the parasitic/delay extraction at POST ROUTE stage. Then use Modelsim/NCSIM or whatever the preferred RTL simulator to verify it (like we normally do in gate-level simulation). This is the easiest thing to do if you do not want to struggle in transistor-level simulation.

If you want to see the impact of your digital layout on the analog side (glitching, coupling etc), then you have to import the full design in Vertuoso.

Cheers