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LVS Fails when PEX_RUN set to TRUE

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sonofflynn

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I cannnot pass Calibre LVS on my APR block when the environment variable PEX_RUN is set to true. The design does pass lvs when PEX_RUN is set to false, however. Does anyone know why this might happen? Also can someone explain what the PEX_RUN environment variable does?
 

hsj

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Hi,
I think.. The definition in the rule file could be different when you run lvs and xrc.
maybe, you should check the PEX_RUN of #IFDEF or #IFNDEF statement if it has that.

BR,
hsj
 

saurabhr8here

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I have some experience in this field and I believe PEX_RUN variable enables or disables creation of extraction layer translation. So once your LVS completes, if PEX_RUN is set to true, all the CAD layers from your layers are mapped to physical layers that are in the technology file (transistors, vias, metals) for RC extraction. I think that your LVS fails when you turn on PEX_RUN to true because Calibre is not able to map the CAD layers to the correct technology layers. Check and see the technology mapping file to ensure that all the CAD layers are correctly mapped.
 

process_geek

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I have some experience in this field and I believe PEX_RUN variable enables or disables creation of extraction layer translation. So once your LVS completes, if PEX_RUN is set to true, all the CAD layers from your layers are mapped to physical layers that are in the technology file (transistors, vias, metals) for RC extraction. I think that your LVS fails when you turn on PEX_RUN to true because Calibre is not able to map the CAD layers to the correct technology layers. Check and see the technology mapping file to ensure that all the CAD layers are correctly mapped.
Hey Saurabh to remind you the techfile that would be included for running either LVS or Extraction are same. So there is no question of any layer missing since the same set of layers are used. Extraction will be using addition files for calculating addition parameters like NRD,NRS,SA,SB,SC,SCA,SCB etc, using those layers only which are there in common technology file.

if you are working on lower technology nodes DFM comes into the picture and its turned on only when you are doing extraction since it considers all parameters like poly rounding, OD rounding, stack gate, contact placement effect etc so make sure that your DFM switch is off while you are doing LVS since DFM considers all these effects and will reduce the effective length of POLY or width of OD so LVS will surely fail. Other way is say your POLY length got reduced by x% then you can set the TOLERANCE FACTOR accordingly which neglects slight deviation of L or W. You can observe the extracted netlist to verify this fact. If you are still unable to figure it out i am there to help.
 

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