lvs error for resistor

[vashistha]

I have to make a layout of 200k resistor so i connected 20 resistors in series,10k each. But when i done lvs it will give a property error.
PROPERTY ERRORS
DISC# LAYOUT SOURCE ERROR
1 0(1.055,0.705) r18 R
m: 1 m: ? (reduced instance)
Why so?

 

[Dominik Przyborowski]

If it is an Assura error, check if You have switch sthing like SBAR_FEATURE. In some pdks resistors with multiple bars are "strangely" treated.

 

[vashistha]

i am using calibre

 

[erikl]

i am using calibre

Marking layer missing?

Perhaps the proper instructions for series (and parallel) resistors extraction and comparison are missing in your Calibre PEX/LVS rules' set? Check it!

Work-around:

1. use 20 series resistors in your schematic

or - if not enough space there -

2. create a sub-cell for these 20 series-connected resistors, i.e. a schematic, symbol and lvs symbol for it, and instance the symbol in the original schematic.

 

[vashistha]

i am using unsalicided pplus resistor, it has three terminals (plus minus sub). How i make the sub terminal in layout.Is sub terminal connected to ground

 

[erikl]

Is sub terminal connected to ground

Yes, right!

 

[AMSA84]

Why don't you use the Layout XL?