LVS error for parameter mismatch

[bhaveshsoni]

parameter mismatch error is coming after LVS run
these error is shown at that transistor where I am use finger more than one.
Plese help me for solution of these error
I am using cadence 514 tool
Thanx

 

[dgnani]

It could be a mismatch in the number of fingers, some LVS decks check for it, try changing the number of fingers in the schematic for one of the devices flagged as mismatched
Otherwise provide more details:
what LVS tool are you using? Assura, Calibre,...?
what process/PDK?

 

[bhaveshsoni]

I am using Assura tool for LVS checking
PDK is process
My trasistor size is more than 100u and I am working in UMC 180nm
so it support maximum width upto 100u
so for setting up 200u I am use finger 2
so that is not supported by assura LVS checking
what is the solution ?
Thanx

 

[dgnani]

all I asked was to check that the number of finger was the same in the schematic and in the layout

 

[bhaveshsoni]

ya it is same

 

[dgnani]

what does your error message says exactly?

 

[bhaveshsoni]

error messagearameter mismatch
These error is come to those transistor in which I am use finger size more than 1 in schematic and layout