No result from your suggestion erikl...Let me be more specific with my problem :
LVS debug environment details gives the following description :
FET1comp has mismatched parameter(s):"w" layout: 1.5e-05 schematic: 7.5e-06
For the above description,in my design i have a transistor with Wtotal=15um and multiplicity factor m=2 (thus 2 fets in parallel with 7.5um width each),well,assura can make the correct computation for the layout and it shows the actual Wtotal but it cannot estimate the correct value for the Wtotal for the side of the schematic (it seems considering m=1 always independent from the value i have set in the fet properties).
There must be a way to deal with this error,or else why cadence gives us the opportunity to use multiplicity factor?