LVS error concerning multiplicity of tranistors

[jimito13]

Hi,

I am getting this LVS error for the transistors that i have in my design with multiplicity (NOT fingers).

FET1comp has mismatched parameter(s):"w" layout: 1.5e-05 schematic: 7.5e-06

How can i tell assura to merge these parallel transistors?I found the mergeparallel switch but i can't find the correct syntax...Manual also doesn's say anything that clarifies the situation.

I would appreciate any helpful answer.Thanks in advance.

 

[oversea]

Better use bus instead of multiplicity. Even you pass the LVS, you can encounter problems with Assura extraction. Or you may want to try "MULTI" layer which defines multiplicity.

 

[jimito13]

What is bus??I assume it is the alternative way to define multiplicity with the expression M<1:N>,right?I read somewhere that this works but why we are given the multiplicity choise since it causes errors,there must be a way to avoid all these annoying errors from LVS,or extraction.

 

[erikl]

... but i can't find the correct syntax.

Perhaps the assuraLVS.rul from C@dence' GPDK446 may help?

 

[jimito13]

erikl thanks for the pdf but the syntax proposed in the assura GUI is completely different.This is the proposed syntax for the mergeParallel function :

mergeParallel( {device | "device_name") {noMerge|merge} [SKILL_function])

From all these arguments the only one that i can set correctly is the "device_name".The others in every combination i tried make the simulator result error before LVS even starts up!I checked the manual of Assura and they don't give an example.Have you or somebody else ever met this problem and how should i deal with it?Thanks in advance again.

 

[erikl]

Perhaps you can find the needed [SKILL_function] in your assuraLVS.rul file? Something like the parallelMOS shown in the PDF above?

 

[jimito13]

Ok,i will check it out.Thank you

 

[jimito13]

No result from your suggestion erikl...Let me be more specific with my problem :

LVS debug environment details gives the following description :

FET1comp has mismatched parameter(s):"w" layout: 1.5e-05 schematic: 7.5e-06

For the above description,in my design i have a transistor with Wtotal=15um and multiplicity factor m=2 (thus 2 fets in parallel with 7.5um width each),well,assura can make the correct computation for the layout and it shows the actual Wtotal but it cannot estimate the correct value for the Wtotal for the side of the schematic (it seems considering m=1 always independent from the value i have set in the fet properties).

There must be a way to deal with this error,or else why cadence gives us the opportunity to use multiplicity factor?

 

[nsccad]

Yes, Assura should be supported. The default function mergeParallel() from Assura does not support that. You will need to write your own SKILL code to merge to the Wtotal. You could merge the W parameter when W1== W2 and Wtotal=W1+W2.

Added after 2 minutes:

jimeece13,

PM me, i will tried to send you the SKILL code.

 

[erikl]

Re: LVS error concerning multiplicity of transistors

... FET1comp has mismatched parameter(s):"w" layout: 1.5e-05 schematic: 7.5e-06
...
For the above description,in my design i have a transistor with Wtotal=15um and multiplicity factor m=2 (thus 2 fets in parallel with 7.5um width each)

In my C@dence setup, a schematic MOSFET with w=15 & m=2 means 2 transistors with w=15, i.e. Wtotal=30. May be this is similar with your setUp?

 

[jimito13]

In my previous post :

For the above description,in my design i have a transistor with Wtotal=15um and multiplicity factor m=2 (thus 2 fets in parallel with 7.5um width each)

What is the difference with your setup erikl??It is the same thing...

This is my setup in cadence :

Width Single Finger : 7.5u
Width All Fingers :7.5u
Fingers :1
Multiplicity :2

Thus,Wtotal=15u as i mentioned earlier.

 

[jimito13]

The compare file of my pdk has the following function for the error that gives me the LVS debug environment :

procedure( FET1comp(m1, m2)
let((paraminfolist )
paraminfolist='(
("l" "abs_comp" "if(BentGate<0.5 then hgp else hgp7)")
("w" "abs_comp" "if(BentGate<0.5 then hgp else hgp7)")
)
unless(getValCase(m1 "m") m1->m=1)
unless(getValCase(m2 "m") m2->m=1)
unless(getValCase(m1 "idg") m1->idg=0)
unless(getValCase(m2 "idg") m2->idg=0)
if( (m1->idg && abs_comp(m1->idg 0 0.5)) then
m1->w = getValCase(m1 "w") * getValCase(m1 "m") )
if( (m2->idg && abs_comp(m2->idg 0 0.5)) then
m2->w = getValCase(m2 "w") * getValCase(m2 "m") )
unless(getValCase(m1 "bentgate") m1->bentgate=0)
unless(getValCase(m2 "bentgate") m2->bentgate=0)
BentGate = m1->bentgate + m2->bentgate
genericcomp("FET1comp" m1 m2 paraminfolist)
)
)

Can somebody see what is wrong and propose me a solution?I have very few knowledge in programming and coding and i can't do it myself...Thanks in advance...