LVS assura error "Unbound Pin"

[KipD]

Hi,

I'm currently completing my first layout, and getting errors on all my pins. When I run LVS I am getting an error on each saying "Unbound Pin".

I have simply placed the pins that were automatically generated in layout XL (when I generated the layout from schematic) within the appropriate metal layer. When I purposefully place them on the wrong metal they blink, so I'm sure they are linked to the schematic.

I am sure there is a very simple explanation for this.. but just struggling to get to the bottom of it.

Many thanks,

Kyle

 

[kemiyun]

Check the layer, it should be the pin layer of the metal you are placing them. At least it was like this for TSMC pdks.

 

[KipD]

Check the layer, it should be the pin layer of the metal you are placing them. At least it was like this for TSMC pdks.

Thanks kemiyun. The pins are definitely in the pin layer.

 

[kemiyun]

Can you share the LVS log or something, it is very hard to debug with that information. Are there any net errors, have you tried labelling with pin layer? It can be caused by many things, I cannot guarantee a solution but I believe it would be helpful to readers if we could debug this problem.

 

[KipD]

Re: LVS assura error "Unbound Pin"

Can you share the LVS log or something, it is very hard to debug with that information. Are there any net errors, have you tried labelling with pin layer? It can be caused by many things, I cannot guarantee a solution but I believe it would be helpful to readers if we could debug this problem.

Thanks Kemiyun. Yes, I have tried creating labels for the pins.

To make things more simple I have created a schematic with a single transistor and pins attached to each terminal. I have then generate the layout for this and dropped the pins on the appropriate metal contacts of the transistor. I am still getting the error for each pin.

I have attached the LVS log for this. Thanks!

 

[gag2000]

A tip wich work with at least austriamikrisystem, IBM and TSMC, in VXL, when importing design:
- create pin on layer Mx type pin (or Poly or whatever you want, but on a pin layer )
- create label on layer "same as pin" with purpose "same as pin"
During routing, label justification mark must stay over the pin symbol.