Warlike
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Yes, sure.Is the input to your driver full-scale 0-2.5V?
They can't. Vds ~ 1 V for both.Your current source/sink might be going out of saturation
Can you advise me papers or books where described this technique?I usually have a pre-driver with a smaller differential voltage driving the final driver.
I don't know of any papers. What I do is very simple: I use an inverter that does not hit the rails so that the top and bottom current source/sink do not go out of saturation.Can you advise me papers or books where described this technique?
And tell some basically principles of this technique?
Thanks. I would decrease W/L to something like this.Your W/L ratios seem a little too big. In my case (up to 1.8GHz), I use 60/0.5 for PMOS and 40/0.5 for NMOS. The current sources are 480/1.2 for PMOS and 412/1.2 but, of course, it depends on the process you are using.
Can you explain?inverter that does not hit the rails
But when modeling transient process there are distortion at the moment of switching. Vos, Voh, Vol go up or down about 50-100 mV
I will post picture tomorrow.If I understand this correctly, both inputs and the vcm (of course) are wiggling
Hm... I thought that CMFB should correct Vos only over the PVT variations, i.e. CMFB frequency should be low and loop should be stable (phase margin > 60 deg) and have large gain. It is not correct?Doesn't that mean that you have CMFB issue?. Does that happen at any frequency? Could it be a too slow CMFB? what is its BW?
OK, this is the problem! The CMFB BW should be very large, it has to correct for common-mode variation changes at speed and of course, it will work over PVT.Hm... I thought that CMFB should correct Vos only over the PVT variations, i.e. CMFB frequency should be low and loop should be stable (phase margin > 60 deg) and have large gain. It is not correct?
Ok. I will verify it tomorrow. But can you tell me what bandwidth I should targer for? And I'm not sure that it is correct (that BW should be large).OK, this is the problem! The CMFB BW should be very large, it has to correct for common-mode variation changes at speed and of course, it will work over PVT.
Authors said that CMFB amplifier is low BW. Or I didn't understand it correct?In the amplifier, the first stage's output impedance is high, which in combination with the Miller capacitor creates a low frequency pole. Thus low frequency pole decides the bandwidth of the feedback amplifier. Therefore, without any compensationin feedback network, this low bandwidth diffamp. provides good phase margin even for a wide range of Load (from 0 to 10pf).
Vds of switches should be low? Now I tuned it to ~(80-90) mV for PMOS and ~(20-30) mV for NMOS. Is it correct? What are principles of Vds of switches tuning? Should it be match or not?
What is inverter that does not hit the rails?
Thanks. But switch should be in triode region?The switch is on/off so its vds does not matter, it just has to be big enough to carry the current.
It does not matter!But switch should be in triode region?
Pretty much the same.Could you tell me techology node for that you gave examples of W/L? Process I used is 180 nm with thick oxide and power supply is 2.5. Should W/L be something like yours?
One paper I have based my TX I attached above.
Ok. Can you advise me papers where used another CMFB implementation?I never saw that cmfb implementation before but I would think that the bw of the amp still needs to be large.
The paper by Boni is what is commonly used as cmfb.Ok. Can you advise me papers where used another CMFB implementation?
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