LVDS-SPI isolation methods/ideas?

[zoulzubazz]

hello everyone,

The circuit i am currently working with an INTAN IC which transmits data using an LVDS SPI bus. Isolating a normal SPI bus is straight forward if one of the many digital isolator packages are used. However isolating LVDS-SPI seems to be a bit more challenging. Is there a way to achieve this without having to convert LVDS-SPI to CMOS-level-SPI and then back to LVDS-SPI.

Also if the two step conversion method (mentioned above) is adopted what precautions should be taken to reduce timing errors, caused due to the propagation delays in ICs used to do the above mentioned conversions. Thanks very much.

 

[Analog Ground]

First question about not having to first convert to single-ended. Most probably "no". Second question. Go with parts from Analog Devices and/or Linear Technology. They have high performance solutions for the conversion and isolation. Here is something to help get you started.
https://www.analog.com/en/circuits-from-the-lab/cn0256/vc.html
https://www.linear.com/product/LTM2883

 

[FvM]

Propagation delay and delay skew will be mainly determined by the digital couplers. NVE magnetoresistive and TI capacitive couplers give best performance among recent products.

I'm not aware of dedicated LVDS isolators. I guess they aren't made because the speed range provided by the LVDS standard can't be maintained through an isolator.

What's your intended bit rate? The only master sided clock topology of a standard SPI interface restricts a reasonable SPI speed over isolation to maximum values around 10 MHZ.

 

[zoulzubazz]

hey apologies for the delayed reply. The data rate envisaged is 15.5 Mbits/s. NVE IL262 fits the purpose, and the maximum propagation delay from various ic's including the IL262 used for up and down conversion from SPI to LVDS is about 16ns. will this amount of delay lead to timing errors at a data rate of 15.5Mbits/s?
from my understanding 1/4th of the clock period should be greater than the propagation delay(please correct me if i am wrong) to avoid timing errors. @ 10Mhz as FvM pointed out, 1/4th of the clock period is 25ns which is greater than 16ns propagation delay expected in the system. again please correct me if any of this is wrong. thanks very much.

 

[FvM]

There are several ways to increase the speed of an SPI bus despite of delay times. Which are available for your design depends on SPI master features and if you have control about it. Late sampling of MISO data is e.g. provided by most microcontroller SPI interfaces and should be no problem in a FPGA based interface. Ultimately SPI can be designed with a separate return clock.