Source synchronous data transfer with embedded clock is a popular method for fast serial interfaces (Ethernet, USB, SATA, PCIE). But it requires to extract the receiver clock from the data stream. CDR (clock and data recovery) is supported by Gigabit transceivers with respective FPGA series, for links in the lower speed range (e.g. some 100 MBPS) you need to set up your own clock extraction respectively synchronizer circuit, e.g. a software PLL. Or use oversampling clock on the receiver side.