As the device manual states, the actual assignment of high and low speed pins can be found in the pinout file. It's also shown in Quartus pin planner tool.
If you look at the device datasheet, you get the impression that the differences between nominal low and high speed pins are marginal and irrelevant for 95 % of applications. Other than stated above in post #2, it's not related to availability of LVDS IO standard in the respective banks. But there may be differences for other IO standards that I didn't yet use in MAX10 designs.
Any IO pin can be used for slow SPI interfaces. A 5.5 MHz SPI clock will be usually a logic generated signal rather than a PLL clock output, thus there's no purpose of using dedicated clock outputs.