Low power optimisations

[dynamicdude]

What is the procedure to insert level shifters in Multiple voltage designs?

And people who have worked in Low power optimisation, can you give me which technique you have seen as best when it comes to power reduction at 90nm and below.

 

[joe2moon]

Basically, the tool needs to know the from-to voltage domain pair of specific level shifter.
After that, you should able to instruct the tool where to insert those level shifters.
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Currently, the logic synthesis tools and P&R tools have the ability to insert level shifters during the synthesis or post-process gate-level netlist and insert level shifters at nets which are cross-voltage domains.

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Power reduction techniques:
- Clock gating(for dynamic power) & Multi-Vth (for leakage power) are most popular/mature methods used to reduce the power consumption.
Most of synthesis tools and P&R tools have supported them well.

- Multi-Vdd design
Can also reduce power consumption.
Traditionally, this is done manually; and more ane more EDA tools support this right now.

- Memory slicing

- Power-gating

 

[dynamicdude]

Can you throw some light on Power gating and Memory slicing techniques??

Are they supported by tools or shd be done manually?

 

[joe2moon]

1) Power Gating
- State Retention Power Gating(SRPG) register
--> Already supported by library venders & synthesis tools.

- 1.a) Fine grain power gating
Power switch is bulit-in the standard cell.
--> Already supported by library verders and P&R tools.

- 1.b) Coarse grain power gating
Power gating at block-level.
--> Used to implement manually.
--> But should be supported by tools in the near future.

2) Memory Slicing
- As far as I know, it should be done manually.
Since it puts impact not only on power consumption but also on timing, area and floorplan.

 

[kimthi]

U can find out from Magma aplication note.

 

[avimit]

At 90nm apart from multi vdd following would help
1). clock gating: can be performed automatically by design compiler, look man page for 'insert_clock_gating'
2). Mising multi vt cells would help, so that if a path is slower, high vt cells may be used to save power, as they have less leakage
3). Isolating power, i.e complete shut of a power to a block when not in use would help
4). Minimising transition through your logic design would help.
5). have a look at
http://www.vlsiip.com/low_power.html for some tips.
Hope it helps,
Kr,
Avi
http://www.vlsiip.com