Basically, the tool needs to know the from-to voltage domain pair of specific level shifter.
After that, you should able to instruct the tool where to insert those level shifters.
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Currently, the logic synthesis tools and P&R tools have the ability to insert level shifters during the synthesis or post-process gate-level netlist and insert level shifters at nets which are cross-voltage domains.
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Power reduction techniques:
- Clock gating(for dynamic power) & Multi-Vth (for leakage power) are most popular/mature methods used to reduce the power consumption.
Most of synthesis tools and P&R tools have supported them well.
- Multi-Vdd design
Can also reduce power consumption.
Traditionally, this is done manually; and more ane more EDA tools support this right now.
- Memory slicing
- Power-gating