In logic synthesis, it is hard to describe the power intent. You usually deal with blocks during logic synthesis, but you are interested in measuring the power of all blocks at the same time. They only really exist at the same time in the SoC, meaning during physical synthesis.
It is true that you can write a UPF file and pass that to logic synthesis. It is not impossible. But that file is helpful for setting corners and maybe some retention/level shifter settings. It does not help you to determine the power consumption of the SoC in its many possible functional configurations.