Low power design : Active-Low or Active-High Reset ?

[omara007]

active low reset

Hi folks ..

Which is better for low power design : Active low reset OR active high reset ? .. and why ?

 

[semi_jl]

active high reset

They will affect the power consumption?

I am confused with it ...

 

[omara007]

active low reset circuit

They will affect the power consumption?

I am confused with it ...

Yes, Reset (being active low or active high) affects the power consumption differently.

 

[FvM]

reset active low

Do you have any idea, why power consumption should be different with CMOS logic? I don't. I guess, that you are not talking of creating TTL ASICs?

 

[omara007]

why active low reset

Do you have any idea, why power consumption should be different with CMOS logic? I don't. I guess, that you are not talking of creating TTL ASICs?

No. I'm talking about CMOS.

 

[omara007]

active low active high reset

any new contributers ?

 

[FvM]

high reset

There is no effect for CMOS circuits.

 

[omara007]

why is reset active low

There is no effect for CMOS circuits.

do you think it's the same from the power consumption point of view when the inactive reset is always high (in the active low reset) .. and when it's always low (in the active high reset) ?

in one case, the reset will stay logic '1' for most of the time and in the other it will stay logic 'o' ..

keep in mind that reset , in most cases, goes to every single part of the design ..

 

[rjainv]

active low reset

are you thinking that power dissipation would be more because capacitors storing the charge to denote logic "1" would not be perfect and would be leaky ?

 

[iwpia50s]

active high + active low resets

Reset being active high or active low only impacts leakage, which is why active low is most commonly used.

 

[rjainv]

reset power high or power low

Reset being active high or active low only impacts leakage, which is why active low is most commonly used.

isn't reset going to be inactive for most of the time and keeping a high value cause more leakage ??
if so, then how does a active low reset help in reducing leakage ?

 

[omara007]

asic active low reset

Reset being active high or active low only impacts leakage, which is why active low is most commonly used.

isn't reset going to be inactive for most of the time and keeping a high value cause more leakage ??
if so, then how does a active low reset help in reducing leakage ?

rjainv .. you have a valuable statement .. it looks like it's better to use active high reset in case you want to save power .. am I correct guys ?

 

[omara007]

active low/high timing

Any new comments regarding which RESET is better from the low-power consumption point of view (Active-High or Active-Low) ?

 

[onlymusic16]

simple cmos power on reset design

Reset being active high or active low only impacts leakage, which is why active low is most commonly used.

isn't reset going to be inactive for most of the time and keeping a high value cause more leakage ??
if so, then how does a active low reset help in reducing leakage ?

rjainv .. you have a valuable statement .. it looks like it's better to use active high reset in case you want to save power .. am I correct guys ?

Hi All,

iwpia50s has given the correct explanation. Active low resets are the most commonly used ones.

Regards.

 

[omara007]

active high rc reset

Reset being active high or active low only impacts leakage, which is why active low is most commonly used.

But won't leakage affect the overall power consumption !!

 

[kaustubh.pagedar]

Hi,
I think It's better to keep it active low
Reason may be, Discharging of Capacitor is more faster then charging it(Please refer characteristics of capacitor). I'm not sure just assuming.
Please suggest in case if i'm wrong.

 

[eld03]

lets make it simple : power consumption:
CMOS no effect ~`,
TTL reset High : when not in operation will have to sink 1.6ma and for
TTL reset LOw : not in operation will have to sink 400ua. Now , so find for yourself the merit.

 

[sam33r]

So what is the conclusion?
I always thought resets are active low just because its easy to pull down rather than to pull up.

 

[keith1200rs]

FvM gave the answer over 3 years ago https://www.edaboard.com/threads/121260/#post531100

Resets are active low because they are intended to work while the power rails are rising. The only voltage you can be sure of at that time is zero.

Keith

 

[eld03]

FvM gave the answer over 3 years ago https://www.edaboard.com/threads/121260/#post531100

Resets are active low because they are intended to work while the power rails are rising. The only voltage you can be sure of at that time is zero.

Keith

the issue has to replied in context to low power. what you say is right it helps in power on reset as well.