low frequency clocks generation in xilinx clock wizard

[kommu4946]

Hi all,

I need clocks with frequencies less than 5Mhz,but i am able to generate minimum of 5Mhz through clock wizard for zynq fpga.Is there any way to generate low frequency clocks other than using divider ( i generated required clocks through counters but is it good coding technique?) suggest me if there any other methods possible.

Thanks

 

[ads-ee]

Instead of generating a 5 MHz "clock" generate a 5 MHz enable signal (i.e. a single clock wide pulse that occurs every 200 ns), that is generated using a higher frequency clock.

Regards

 

[kommu4946]

ads-ee , i didn't get you .Some of my modules operates at 1.5 mhz and 1 mhz in that case what i have to do.Can you elabarate

 

[ads-ee]

Ah, I thought you meant you needed a 5 MHz clock and couldn't generate it from the PLL in the Zynq. I read this as but i am NOT able to generate minimum of 5Mhz through clock wizard for zynq fpga. Sorry for misinterpreting you, too many posts are written so poorly I automatically "add" and "translate" words I think are missing or wrong.

What is your input clock? You first need to generate a clock that can be divided down using counters to generate a single clock wide pulse for the 1.5 MHz and the 1.0 MHz enables.
Unless you are starting with a clock that is some multiple of the 1.5MHz you will have to generate the enable using an NCO of some sort (which will introduce jitter, hopefully that can be tolerated).

E.g. If you can generate a 15 MHz clock then you can have the 1.5 MHz counter count between 0-9-0 and the 1 MHz counter counts between 0-14-0. Each time you reach 9 and 14 you generate your enable. So the logic you are running at 1.5 MHz would look like this:

always @ (posedge clk_15m) begin  // uses the same 15 MHz clock that generates the counters and enables
  if (enb_1m5) begin
    // code that runs at 1.5 MHz
  end
end

Regards

 

[kommu4946]

I am fallowing the same method ,but i am using clock enables as clocks for some modules ,Does it make any difference using clock enables as clocks from the method you suggested( running all modules at same clocks but different clock enables).

 

[ads-ee]

Yes there is a big difference one is a synchronous design (using an enable) and the other is not.

 

[kommu4946]

Yes there is a big difference one is a synchronous design (using an enable) and the other is not.

why one with enable is synchronous other is not ,even though both clk_enable_1_5m (if one use clk_enable method) and clock_1_5m s are derived from same clock_15m .Till now i thought that if data transfer occurs between unrelated clock domains(like 100mhz and 33mhz) it is called Asynchronous ..Is multi clock system is always referred Asynchronous design, even though clocks are related frequency? .

 

[ads-ee]

Clocks generated they way you want from counters is considered bad practice because they should be considered asynchronous to the generating clock in the design as they have variable delay (due to different placement and routing) each time you build the FPGA. But go ahead and build designs like that, I'm not stopping you.

 

[verylsi]

HI Ads-ee,

So it is always advisable to use one external clock and design everything using that clock as a base clock and vary the frequencies as per required through well calculated pulses ( enables ) .

Hope I understood correctly. please acknowledge.

Also in some cases the adc clock is in fractions like 6.543 MHZ in such cases how to proceed ? as dcm do not support fractions. DO we need to do the clock corrections through inserting a correction pulse in between and if so, then is it recommended ?

Is it ok to continue this question in the same thread or shall I start a new one ?

 

[ads-ee]

So it is always advisable to use one external clock and design everything using that clock as a base clock and vary the frequencies as per required through well calculated pulses ( enables ) .

I would certainly advise doing this in FPGAs.
The reason is there are limited resources to get onto clock buffers in an FPGA from the fabric. Both Altera and Xilinx both recommend in their documentation to not drive clocks from FFs in the fabric. If the majority of the designs you work with have multiple interfaces with different unrelated clock frequencies then you may wish you didn't use those extra clock domains, as they use a clock buffer (fortunately most of the newer parts have regional clock buffers). While setup time from the base clock to the generated clocks has more timing margin due to the delay in the generated clock path, hold time will suffer and setup time from the generate clock to the base clock will also suffer. Clock skew between the domains can be an issue. If you have multiple generated clocks that are multiples of each other, every place and route run will likely result in different skew between those clocks, which could result in timing violations between those domains.

Also in some cases the adc clock is in fractions like 6.543 MHZ in such cases how to proceed ? as dcm do not support fractions. DO we need to do the clock corrections through inserting a correction pulse in between and if so, then is it recommended ?

Adding lots of jitter to a ADC clock isn't something I recommend doing. You'll end up with artifacts in the digitized output. The usual way would be to either sample at a multiple of your base clock (no added jitter) or use a different clock with good jitter characteristics that is a multiple of the required sample rate.

But like I said before, you can accept or ignore my advice and deal with the consequences of doing so in your own designs.

Regards