Sub-threshold operation is known to have low speed, but I don't see that effect contributing significantly to your problem here. It is primarily the dominant pole being at the pass-transistor gate. If you work out the output impedance, it would be a very high number over a broad frequency range when the load current is at it's lowest (this is regardless of the pass transistor in sub-threshold).
Even if the sub-threshold operation had a telling effect, you just don't have an option to move it to strong inversion by decreasing the pass transistor width (or heavy bleed current) without reducing the peak operational current greatly (or highly inefficient regulator).
You could rather try some of the known techniques to improve load transient response.
1. Rincon-Mora G, Allen P (1998a) A low-voltage, low quiescent current, low drop-out regulator.
IEEE J Solid-State Circuits 33(1):36–44, DOI 10.1109/4.654935
2. Al-Shyoukh M, Lee H, Perez R (2007) A transient-enhanced low-quiescent current low-dropout
regulator with buffer impedance attenuation. IEEE J Solid-State Circuits 42(8):1732–1742,
DOI 10.1109/JSSC.2007.900281
3. Oh W, Bakkaloglu B (2007) A CMOS low-dropout regulator with current-mode feedback buffer
amplifier. IEEE Trans Circuits Syst II, Express Briefs 54(10):922–926, DOI 10.1109/TCSII.
2007.901621
4. Hazucha P, Karnik T, Bloechel B, Parsons C, Finan D, Borkar S (2005) Area-efficient linear
regulator with ultra-fast load regulation. IEEE J Solid-State Circuits 40(4):933–940, DOI
10.1109/JSSC.2004.842831
5. Man TY, Mok P, Chan M (2007) A high slew-rate pushpull output amplifier for low-quiescent
current low-dropout regulators with transient-response improvement. IEEE Trans Circuits Syst
II, Express Briefs 54(9):755–759, DOI 10.1109/TCSII.2007.900347
First confirm that you have a real issue at your hands, as this behavior is expected and goes well with most applications.
Alertlinks, Im not sure how your circuit would solve the problem here, if I'm right, it can only exacerbate it.