low dropout regulator

[lovaraju.ch]

dear saro_k_82

I forgot to mention that I am designing an output capacitor less LDO. whatever the capacitance(Cout) showing in circuit diagram is the parasitic capacitance of the load and which I had taken it as 100 pF. So as you told, the dominant pole was at the op amp output for any load current because it is output capacitor less LDO. And coming to bandwidth there is no much difference between 1 mA-100 mA of load current. At 100 mA, bandwidth is 10 MHz and at 1 mA, it is 8.5 MHz. phase margin wise I had 50-75 deg throughout load range. now could you please extend your discussion after reading these details.

 

[saro_k_82]

The LDO loop is different from other control loops in the sense that it has to correct for any disturbance that arises at the output rather than it's input. A dominant pole at the output would mean first order filtering at the output in addition to a fast loop (containing only non-dominant poles and feed-forward zeros) which provides expected fast and smooth load transient response. In the case where the dominant pole is at the gate of the pass transistor, the load response is dominated by the first pole location of the loop-gain. The load transient response is governed by the output impedance at the frequency of disturbance. At heavy loads, the output impedance is low and at light loads it would be high complicating the response. You can see how an output dominant pole provides good load response due to low output impedance over a broad frequency range.

In other words, a LDO can only source current, sinking is left to the load. So any transient that takes the voltage above the set output level, would then depend on the load time constant and the loop-response time (to sense and stop sourcing current) to drop to or below the correct output level.

 

[lovaraju.ch]

dear saro_k_82

whatever you have discussed is true for any two stage op amp.can we have a solution to this problem. If yes please suggest me. Do you think that sub threshold region of pass transistor under light load condition creates any problem.

 

[saro_k_82]

Sub-threshold operation is known to have low speed, but I don't see that effect contributing significantly to your problem here. It is primarily the dominant pole being at the pass-transistor gate. If you work out the output impedance, it would be a very high number over a broad frequency range when the load current is at it's lowest (this is regardless of the pass transistor in sub-threshold).
Even if the sub-threshold operation had a telling effect, you just don't have an option to move it to strong inversion by decreasing the pass transistor width (or heavy bleed current) without reducing the peak operational current greatly (or highly inefficient regulator).
You could rather try some of the known techniques to improve load transient response.
1. Rincon-Mora G, Allen P (1998a) A low-voltage, low quiescent current, low drop-out regulator.
IEEE J Solid-State Circuits 33(1):36–44, DOI 10.1109/4.654935
2. Al-Shyoukh M, Lee H, Perez R (2007) A transient-enhanced low-quiescent current low-dropout
regulator with buffer impedance attenuation. IEEE J Solid-State Circuits 42(8):1732–1742,
DOI 10.1109/JSSC.2007.900281
3. Oh W, Bakkaloglu B (2007) A CMOS low-dropout regulator with current-mode feedback buffer
amplifier. IEEE Trans Circuits Syst II, Express Briefs 54(10):922–926, DOI 10.1109/TCSII.
2007.901621
4. Hazucha P, Karnik T, Bloechel B, Parsons C, Finan D, Borkar S (2005) Area-efficient linear
regulator with ultra-fast load regulation. IEEE J Solid-State Circuits 40(4):933–940, DOI
10.1109/JSSC.2004.842831
5. Man TY, Mok P, Chan M (2007) A high slew-rate pushpull output amplifier for low-quiescent
current low-dropout regulators with transient-response improvement. IEEE Trans Circuits Syst
II, Express Briefs 54(9):755–759, DOI 10.1109/TCSII.2007.900347

First confirm that you have a real issue at your hands, as this behavior is expected and goes well with most applications.

Alertlinks, Im not sure how your circuit would solve the problem here, if I'm right, it can only exacerbate it.

 

[KerimF]

I usually use a PNP transistor.

 

[analogbeginer]

Hi,
Since amp pole is dominant, can an ac coupled local feedback loop help?

---------- Post added at 09:22 ---------- Previous post was at 07:52 ----------

Hi alterlinks,
Is the cap (connected in red) to move the second pole? If so, that wouldnt alter the location of amp pole, so no change in transient. Please correct me if I'm wrong.