You could flatten, "make cell" and assign pins but
you want naming of the master preserved and you
blew away the master, replacing it with polygons
and loose text.
Maybe you want to Make Cell of the flattened data
and then also make a matching cell with the symbol
which once matched, in it with corresponding pins.
Maybe an "lvs" view too, to try and constrain the
levels to match (stop at the flattened rep's instance
rather than drilling down to polygons and wondering
why they don't correspond to busted hierarchy
anymore).
The transistor -master- has not been used. Why this
matters, I couldn't say. Key question is, does the
extracted view find a transistor of proper type (never
mind the name correspondence) or not? If not, then
your flattening process has discarded some sort of
useful information (such as, if you "make cell" from
selected "stuff", any hidden or unselectable layers
may be excluded from that process. Might go into the
original just-flattened layout (or a copy), make all
layers valid, visible and selectable, and see if there's
"stuff" that was in the PCell that didn't make it to
the final flat version, but maybe extract / LVS needs
to function.