Loss of terminal number and component name after flattening of transistor

[adeniyiMokesioluwa]

Good day, All

I am working on a layout. when I intend to extend my Metal1 layer of the transistor, I flatten it and in updating the component in the layout, especially the transistor, we deselect all metals apart from Metal1 to extend it.
However, once this is completed, my hierarchy is lost and the Component name i.e i.e GF_BiCMOS8HP and labeling of the metals. i.e 1; for C; 2 for B; 3 for E can no longer be retrieved .

Hence when I need to compare and update from schematic with the layout, the transistor flattened still appears as if it has not been used on the layout.

I would really appreciate your help with this.

Thanks for your assistance.

 

[rangermad]

First, why are you flattening a pcell? Can you add the metal at the next level? Secondly, you should have the option when flattening a pcell to keep pins. Thirdly, keeping pins will likely create LVS issues.

Rob

 

[dick_freebird]

You could flatten, "make cell" and assign pins but
you want naming of the master preserved and you
blew away the master, replacing it with polygons
and loose text.

Maybe you want to Make Cell of the flattened data
and then also make a matching cell with the symbol
which once matched, in it with corresponding pins.
Maybe an "lvs" view too, to try and constrain the
levels to match (stop at the flattened rep's instance
rather than drilling down to polygons and wondering
why they don't correspond to busted hierarchy
anymore).

The transistor -master- has not been used. Why this
matters, I couldn't say. Key question is, does the
extracted view find a transistor of proper type (never
mind the name correspondence) or not? If not, then
your flattening process has discarded some sort of
useful information (such as, if you "make cell" from
selected "stuff", any hidden or unselectable layers
may be excluded from that process. Might go into the
original just-flattened layout (or a copy), make all
layers valid, visible and selectable, and see if there's
"stuff" that was in the PCell that didn't make it to
the final flat version, but maybe extract / LVS needs
to function.