loop for gates in VHDL

[kongruxue]

Hi, I have a question. now there are 3 vector connect with AND gate like this:

C(3)<= A(4) and B(3)
C(2)<= A(4)and A(3)and B(2)
C(1)<= A(4)and A(3)andA(2)and B(1)
C(0)<= A(4)and A(3)andA(2)andA(1)B(0)

How can I use loop to describe it?

 

[vipinlal]

Use nested for loops for it..

for i in 0 to 3 loop
  for j in i+1 to 4 loop
    t <= a(j) and t;
 end loop;
 c(i) <= t and b(i);
end loop