[SOLVED] lookup table with CPLD or FPGA?

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ahmadagha23

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Hi friends,
I want to implement a lookup table (rom memory) which comprise 362 cells, each one is 16bits ( so contains 2*181*16=5792bits). I prefer to use CPLD because it do not need any PROM in PCB. Can you suggest me a CPLD from XILINX (for example xc9500) that can implement this lookup table and two (16 bits) dividers and two multipliers?

Is it better to use FPGA (SPARTAN2) or cpld?


thanks
 

ur lookup table lut consumption would be far much less than muls and divs itself.
so consider a device which has embedded mul's and div's
 

If you want to design such design without th PROM. Maybe you can try lattice's XP device. It has the same architecture as Xilinx's FPGA, and it contains own FLASH on chip.
 

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