hello i used combinational logic for implementing LUT by using case statements . whatever values i gave are not coming exactly in the simulation. only integer part is coming and fractional part is not comimng . for ex: 5.734 . my simulation is showing only 5 . how do i get the exact values ?
No wonder.i got stuck here from so many days
There is nothing wrong with the design other than it doesn't work.you didnt get my question. there is nothing wrong in the design
you didnt get my question. there is nothing wrong in the design . by using case statements i only assigned outputs for corresponding inputs as 0.011,0.087,-0.045,-0.415 . but in the simulation all 0's are coming . do u know how to assign the above numbers in verilog ? please help me out . i got stuck here from so many days
If you are sure that your design is 100% correct try to contact with your's tool manufacturer.
Code Verilog - [expand] 1 2 3 4 5 wire [7:0] sig1; assign sig1 = 0.011; // always assigns 0 to sig1 as only the integer part is assigned wire [7:0] sig2; assign sig2 = 18.0235; // results in the value 8'b 0001_0010 (18 - integer part) being assigned to sig2
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