Lookup table implementation in Verilog

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krishvamsi

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how to implement a function of the following type sb(z) = logb(1 + bz) in a 2 - dimensional lookup table in verilog ?
 

1. Calculate offline the results of your function for ANY possible input.
2. Store the results in a ROM where the input to the function in actually the address.
3. Code this ROM in Verilog just as you would any other ROM.

Good luck.
 
so here i should store inputs in an address register and outputs in a data register right ?
 

Not register - ROM (Read Only Memory).
Your application will drive the address to this ROM (with represent all possible function arguments)
And get the answer from the data-out port that correspond to that particular address.

The LUT trades memory for computation time / complexity.
 

ok now i got it . so what should be my LUT size if i want to compute logarithmic addition of two 8 bit numbers ?
 

So if:
1. The address width is 8 + 8 = 16
2. And each cell stores the result which is n bits wide (you decide how wide should n be).

The size of the LUT in bits is:
2^16 * n

The size of the LUT in bytes is:
(2^16 * n)/8
 

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