Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Dear Sumant, there are countless types of adders, what kind do you want. pls specify. Nevertheless, I paste a fulladder code here
Kr,
avi http://www.vlsiip.com
Library ieee;
Use ieee.std_logic_1164.all;
ENTITY fulladder IS
PORT( A,B,Cin : IN std_logic;
sum,Cout: OUT std_logic);
END ENTITY;
ARCHITECTURE functional OF fulladder IS
BEGIN
PROCESS(A,B,Cin)
BEGIN
If (Cin = '0' and A = '0' and B = '0' ) then
sum<= '0'; Cout <= '0';
elsif(Cin = '0' and A = '0' and B = '1') then
sum <= '1' ; Cout <= '0';
elsif(Cin = '0' and A = '1' and B = '0' ) then
sum <= '1' ; Cout <= '0';
elsif(Cin = '0' and A = '1' and B = '1' ) then
sum<= '0'; Cout <= '1';
elsif(Cin = '1' and A = '0' and B = '0' ) then
sum <= '1' ; Cout <= '0';
elsif(Cin = '1' and A = '0' and B = '1' ) then
sum<= '0'; Cout <= '1';
elsif(Cin = '1' and A = '1' and B = '0' ) then
sum<= '0'; Cout <= '1';
elsif(Cin = '1' and A = '1' and B = '1' ) then
sum <= '1' ; Cout <= '1';
else
sum <= 'X' ; Cout <= 'X';
end if;
END PROCESS;
END functional;
this would be the simplest and the best implementation.
if u r using any synthesis tool it can infer the adder u want(not for FPGA though,only for ASIC)
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.