VHDL/Verilog simultation
ModelSim is an excellent simulator but the user interface is frustrating for newbies. First of all, I closed all those little windows except for Workspace, Transcript, and Wave. Then I wrote a couple of "do" scripts that make it much easier to create a new project and to quickly rerun the simulation after I edit my design. I added a "reload" button to the toolbar. I can now create a new Verilog project, simulate, edit the source (I use an external editor), and re-simulate, all in less than one minute without clicking or typing anything in ModelSim except my "reload" button. All my simulation controls are stored conveniently in my Verilog testbench, instead of some global ModelSim config file. I'm using convenience features that are included in ModelSim SE but not in ModelSim PE.
SE costs about $20K US. PE costs about $5K. There's a cheaper (free?) XE version that comes with the Xilinx ISE, but I've never tried it.