adpll vhdl
janarthanan said:
i need vhdl/verilog code for adpll. Adpll may have any architecture,
kindly help me
thanks in advance
this is the code u can use
DPLL -- MOORE MACHINE
//=================================================================================
// Title : DPLL
// File Name : dpll.v
// Project : USB 1.1
// Description : Behavioral
//
// Date By version Change description
//=================================================================================
//
//=================================================================================
//
//
//===============================================================================
//"Output of dpll" -- clk_rcv
//"Clock" -- DPLL clock
//"rcv" -- Input to nrzi decoder
//===============================================================================
module dpll(clk_rcv,rcv,clk_high,rst);
output clk_rcv; // Clock output of DPLL
input rcv,clk_high,rst; // rcv -- Input to DPLL
// clk_high -- 48MHz clock
reg a,b,clk_rcv;
parameter [3:0]sc = 4'b1100;
parameter [3:0]sd = 4'b1101;
parameter [3:0]s5 = 4'b0101;
parameter [3:0]s7 = 4'b0111;
parameter [3:0]s6 = 4'b0110;
parameter [3:0]s4 = 4'b0100;
parameter [3:0]s1 = 4'b0001;
parameter [3:0]s3 = 4'b0011;
parameter [3:0]s2 = 4'b0010;
parameter [3:0]s0 = 4'b0000;
parameter [3:0]sb = 4'b1011;
parameter [3:0]sf = 4'b1111;
reg [3:0] state;
reg [1:0]t;
always
begin
@ (posedge clk_high);
a= rcv;
end
always
begin
@ (negedge clk_high);
b=rcv;
end
always @ (posedge clk_high)
begin
if(rst)
state=sc;
else
begin
case (state)
sc:begin
if (b)
state=sc;
else
state=sd;
end
sd:begin
if(b)
state=s5;
else
state=sd;
end
s5: state=s7;
s7:begin
if(a)
state=s6;
else
state=sb;
end
s6:begin
if(b)
state=s4;
else
state=s1;
end
s4:begin
if(b)
state=s5;
else
state=s1;
end
s1: state=s3;
s3:begin
if(a)
state=sf;
else
state=s2;
end
s2:begin
if(b)
state=s5;
else
state=s0;
end
s0:begin
if(b)
state=s5;
else
state=s1;
end
sb: state=s2;
sf: state=s6;
default: state=sc;
endcase
end
end
always @ (state or a or b)
begin
t={a,b};
case (state)
sc:begin
casex(t)
2'bx1:clk_rcv=1'b0;
default:clk_rcv=1'b0;
endcase
end
sd:begin
casex(t)
2'bx1:clk_rcv=1'b0;
default:clk_rcv=1'b0;
endcase
end
s5:clk_rcv=1'b0;
s7:begin
casex(t)
2'b1x:clk_rcv=1'b1;
default:clk_rcv=1'b1;
endcase
end
s4:begin
casex(t)
2'bx1:clk_rcv=1'b0;
default:clk_rcv=1'b0;
endcase
end
s1:clk_rcv=1'b1;
s3:begin
casex(t)
2'b0x:clk_rcv=1'b1;
default:clk_rcv=1'b1;
endcase
end
s2:begin
casex(t)
2'bx0:clk_rcv=1'b0;
default:clk_rcv=1'b0;
endcase
end
s0:begin
casex(t)
2'bx0:clk_rcv=1'b0;
default:clk_rcv=1'b0;
endcase
end
sb:clk_rcv=1'b1;
sf:clk_rcv=1'b1;
endcase
end
endmodule