Looking for layout of test structures

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bjerkely

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I need some layout examples for testing purpose.

I have to design some caps, transistors etc. and then I want to measure some parameters like contact resistance, carrier mobility, conductivity, treshold voltage etc.


Thanx in advance...
 

all this can be found from the fab in which your project tape out.

Thanks and best regards
 

Areky_qin said:
all this can be found from the fab in which your project tape out.
Click to expand...


Thank you,but what I'm doing is not a CMOS device and It will not be fabricated by a facility, It's a lab project.

regards...
 

I've found a useful file, I'm uploading it, maybe someone else needs such information.
 

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