Looking for info about verification languages and tools

[dariush]

Verification

Hi
I want to know more about verification languages,tools?
and its usage in systems design?

 

[eziggurat]

Re: Verification

Try looking into Specman 'e', Solidfy, vera and also sugar.

 

[chipper]

Verification

Specman 'e'?
which software is corresponding

 

[arunragavan]

Re: Verification

check this out

**broken link removed**

might be useful for verification purpose..

with regards

 

[eziggurat]

Re: Verification

You should look at the verification guild if you want some more anwsers in the topic.

www.janick.bergeron.com

I have some good notes on Specman E but I dont have a scanner.

sugar: **broken link removed**

 

[haoboy]

Verification

systemC

 

[yeewang]

Verification

everything, verilog, systemC, vera, e, just depends on how good the person is....

 

[zhangpengyu]

Verification

I think e is best,also you could use systemverilog.

 

[ram]

Verification

there are following methods you can use for verification
1. Specman E language based
2. SystemC based (cadence supports mixed lang.)
3. Arm based
4. VHDL or verilog based
5. SystemVerilog based.

 

[nand_gates]

Re: Verification

How about TestBuilder??
No one has mensioned it here??

 

[haoboy]

Verification

system c is good for system verification

 

[masm]

Verification

DUT
BDD
Formal verification

 

[speedoak]

Re: Verification

Hi
I want to know more about verification languages,tools?
and its usage in systems design?

check this book
Write testbenches, FUnctional verification of HDL model
Janick Bergeron

It is really a good book for HDL verification

 

[vibhute_r_p]

Verification

Also see Digital logic testing & simulation book

 

[weilijun]

Re: Verification

You can also use verilogHDL + PLI to simulate.
A good book to write testbench:
writting testbenches Functional verification of HDL models.

 

[jigjack]

Verification

hi,
e language and specman tool by 'verisity' is one of the best tool to create an automated verification environment.

 

[sarath51]

Re: Verification

Writing Test Bences second edition,
Verifications OF SOC s and
there is a alarger collection of articles inthis forum

 

[kirankgs]

Verification

U can read "Art of Vrification using Vera" txt.

 

[smith_kang]

Re: Verification

hi
now a days verification is very important in system level design.You can refer Himanshu Bhatnagar and book by Pran Kurup(its methodology,stupid!).as sush verification is neccessry at ech level of abstraction viz behavioral,RTL,gate level,and in physical domain.
Formality by Synopsys is formal verification tool

 

[Prasanna Kumar]

Re: Verification

This might help you,

There are different languages on verification.

The attached pps have few description on verification languages