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Looking for info about verification languages and tools

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Verification

systemC, vera, system verilog, e language etc.
 

Re: Verification

C/C++ systemC vera etc.
 

Re: Verification

SystemVerilog (Unified Hardware Design, Specification and Verification Language): http://www.accellera.org

SystemC: http://www.systemc.org

OpenVera (open source hardware verification language from Synopsys): http://www.open-vera.com/

IEEE P1647 (e) VERIFICATION LANGUAGE (supports by Verisity, now the part of Cadence): **broken link removed**
 

Re: Verification

really depends on how complex your testbench will be, and what is te current status of your project.

Learning a new language will take long. And to use it well, the necessary support is also very importnat, so you will be lucky if your are working for a big company and have potentially more licenses could be sold to.

If your project is already in the middle and you want to change your verification methodology, think of your peoject schedule first.

And if this project is all you want to do, make a fancy testbech with some language that is fresh to you and your team could be risky too. Always think the reusability of a testbench...
 

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