Looking for help of substrate shorts

[Jutinal_Uci]

Hi, I have designed a ADC chip of a school project. But, sadly, when we get the chip back from Mosis, it appears that the resistance between Vdd and Gnd is only 30ohm. Our layout can pass DRC&LVS. We think there must be some substrate shorts in our layout. Is there any method we can figure out the location of short?
Thanks

 

[erikl]

The usual method: heat spot observation through the microscope on an opened package chip, preferably with a heat camera. While looking through the microscope, you slowly increase the current (or the voltage) until you can see a spot - or several of them - which somehow change their appearance: mostly colour, or a slight bulge perhaps.

This is a destructive method, of course - apart from observation through a heat camera. Instead of the latter, you could also apply a thin spray-on film which changes its colour with temperature.

 

[Jutinal_Uci]

The usual method: heat spot observation through the microscope on an opened package chip, preferably with a heat camera. While looking through the microscope, you slowly increase the current (or the voltage) until you can see a spot - or several of them - which somehow change their appearance: mostly colour, or a slight bulge perhaps.

This is a destructive method, of course - apart from observation through a heat camera. Instead of the latter, you could also apply a thin spray-on film which changes its colour with temperature.

Thanks for your help. But, since it is a course object. we do not have microscope or heat camera, i can try but is there any method that I can figure out the short by cadence? Besides, if there exists this kind of shorts, LVS or DRC won't reported such errors, right?

 

[D.A.(Tony)Stewart]

Did your design have any ESD protection or DFT criteria for fault isolation?

Are you familiar with E-field susceptibility on high impedance chips? and EOS safe environment ? deionizer etc.

I remember once using TEK™ differential FET probes with a rating of 25V, which engineers create( burn out) ... just by sneezing without consideration to ESD without grounding high Z, low pF inputs or connected to a low Z source.

A high impedance probe generator/detector with a display of V-I is the best test for this type of failure.
... for fault detection ( a.k.a. Huntron Tracker)
...non destructive if using low current and voltage
... often when a junction fails it shows up with peculiar VI curve and often with more capacitance. Levels tested are usually starting in the uA range.

If it is any consolation, when I started design in the 70's, I used to blow TTL even Mil-Std 883B X-ray inspected TTL IC's before I became aware of EOS/ESD practice. I remember also one Xray inspected Mil-Std-883B Burr Brown 12MHz ADC that failed the monoticity criteria due to the process, whereas the std. Industrial part always passed. I reasoned that a weakness on the Vref & Analog gnd created crosstalk from the ADC Digital current which affected the Vref noise or comparator an offset voltage and created the missing steps near transitions from ...01111 to ...10000 etc. BB could not fix the problem in time, so I stuck with the Industrial part for a mission critical application.

 

[dick_freebird]

If your circuit passes LVS, then first question is, what does
an analog simulation at test conditions give for that resistance
(or rather, Vdd/Idd?)?

Second question is, is this reading consistent unit to unit,
and across power cycles?

Third question, what is the I-V characteristic? Ohmic? Diode-
like (N*Vf, VTP+VTN)? Is it at all hysteretic?

Fourth question, if the reading is not consistent, are you
sure you have no floating digital pins, no output test load
left constantly connected (like, say, a pair of 50-ohm-to-
ground terminations being driven)?

If this is a university project it's surprising that said
university has not one thermal imaging system anywhere
in any department. Ask around.