Re: comparator design
To get very low offset voltages you must probably use several pre-amplifiers before the latched comparator itself. These must have a gain high enough to make the input referred offset voltage of the latched comparator negligible, and you must use switched capacitor techniques to store the offset of the pre-amplifiers. These kinds of techniques are described in the document I posted before.
It is not a good idea to have both PMOS and NMOS input differential pairs, because then the offset voltage will depend on the common-mode of you input voltage (I’m assuming differential input here). Once again, if you use a switched capacitor input network, you can have large input swing, while the common-mode input voltage of your diff pair is always the same (the VCM at which you applied in the sampling phase to the input of the comparator).