but I recommend u ACS HDL Translator.. Current version is 5.6,
it is only a bit buggy because the installer forget to add the TMPDIR environment variable
Has anyone try to use Altavista BabelFish translator. Well, it helps us to understand a liitle bit the document but it is not quite right ! Verilog and VHDL have different feature. The tool only translates the syntax not the whole beauty essence of the design. Recommend only for quick solution, designer need to be involved for tune up.