jutek
Full Member level 4
hello
i need your help with this problem. attached picture presents ldo's time response when the output voltage is reprogrammedform 0.8 to 1.4 and vice versa.
it's the simplest ldo with OTA + PMOS and feedback resistors.
as you can see. the falling time is not symetrical with rising one. the blue curve is a pass device's current. so is this falling time related to output capacitor and rds_pass?
if so, i can only decrease output capacity value, but it means, the zero related to it, will go to high frequencies.
what else i can do it or what else can make this falling time so long?
regards
i need your help with this problem. attached picture presents ldo's time response when the output voltage is reprogrammedform 0.8 to 1.4 and vice versa.
it's the simplest ldo with OTA + PMOS and feedback resistors.
as you can see. the falling time is not symetrical with rising one. the blue curve is a pass device's current. so is this falling time related to output capacitor and rds_pass?
if so, i can only decrease output capacity value, but it means, the zero related to it, will go to high frequencies.
what else i can do it or what else can make this falling time so long?
regards