[SOLVED] Logics on generated clock, timing issue?

[legendbb]

Dear experts,

I have a design needs to run on variable clock rates (400KHz to 100MHz). Currently I use a generated clock from counter logic.

I am thinking about using the generated clock to connect directly to those dependent logics (not very big, just some shift registers and FSMs).

I understood when clock is fast > 20MHz, generated clock is not a good practice (probably due to clock routing). Should I look into configurable clock generator or try on small logic first?

Please share you professional opinion.

Regards,

 

[TrickyDicky]

You should never get into the habit of using logic generated clocks in FPGAs. You should generate clock enables isntead.

 

[legendbb]

You should never get into the habit of using logic generated clocks in FPGAs. You should generate clock enables isntead.

Thank you for your comment.